1. Field of the Invention
The present invention relates to silicon carbide layers and, more particularly to a method of forming silicon carbide layers.
2. Description of the Background Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit densities. The demands for greater circuit densities necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g., sub-micron dimensions), the materials used to fabricate such components contribute to the electrical performance of such components. For example, low resistivity metal interconnects (e.g., aluminum and copper) provide conductive paths between the components on integrated circuits.
Typically, the metal interconnects are electrically isolated from each other by an insulating material. When the distance between adjacent metal interconnects and/or the thickness of the insulating material has sub-micron dimensions, capacitive coupling potentially occurs between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit. In order to minimize capacitive coupling between adjacent metal interconnects, low dielectric constant (low k) insulating materials (e.g., dielectric constants less than about 5.0) are needed.
In addition, a barrier layer often separates the metal interconnects from the low dielectric constant (low k) insulating materials. The barrier layer minimizes the diffusion of the metal into the insulating material. Diffusion of the metal into the insulating material is undesirable because such diffusion can affect the electrical performance of the integrated circuit, or render it inoperative.
The demands for greater integrated circuit densities also impose demands on the process sequences used for integrated circuit manufacture. For example, in process sequences using conventional lithographic techniques, a layer of energy sensitive resist is formed over a stack of material layers on a substrate. Many of these underlying material layers are reflective to ultraviolet light. Such reflections can distort the dimensions of features such as lines and visa that are formed in the energy sensitive resist material.
One technique proposed to minimize reflections from an underlying material layer uses an anti-reflective coating (ARC). The ARC is formed over the reflective material layer prior to resist patterning. The ARC suppresses the reflections off the underlying material layer during resist imaging, providing accurate pattern replication in the layer of energy sensitive resist.
Silicon carbide (SiC) has been suggested for use as a barrier layer and/or ARC on integrated circuits, since silicon carbides can have a low dielectric constant (dielectric constant less than about 5.0), are good diffusion barriers and can have good light absorption properties.
However, silicon carbide barrier layers are typically formed using chemical vapor deposition (CVD) techniques. SiC layers formed using CVD techniques tend to have a high oxygen content (e.g., oxygen content greater than about 4%). A high oxygen content is undesirable because it may enhance the diffusion of metals such as, for example, copper, from the metal interconnects through the SiC layer into the insulating material.
Therefore, a need exists in the art for a method of forming a reliable SiC diffusion barrier for integrated circuit fabrication. Particularly desirable would be a SiC diffusion barrier that is also an ARC.
A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture including a silicon source, a carbon source, and an inert gas in the presence of an electric field. The electric field is generated using mixed frequency radio frequency (RF) power.
The silicon carbide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the silicon carbide layer is used as a hardmask for fabricating integrated circuit structures such as, for example, a damascene structure. For such an embodiment, a preferred process sequence includes depositing a silicon carbide layer on a substrate. After the silicon carbide layer is deposited on the substrate, a pattern is defined therein. Thereafter, the integrated circuit structure is fabricated by transferring the pattern defined in the silicon carbide layer into the substrate using the silicon carbide layer as a hardmask.
In another integrated circuit fabrication process, the silicon carbide layer is used as an anti-reflective coating (ARC) for DUV lithography. For such an embodiment, a preferred process sequence includes forming the silicon carbide layer on a substrate. The silicon carbide layer has a refractive index (n) in a range of about 1.7 to about 2.1 and an absorption coefficient (xcexa) in a range of about 0.1 to about 0.7 at wavelengths less than about 250 nm. The refractive index (n) and the absorption coefficient (xcexa) for the silicon carbide layer are tunable, in that they can be varied in the desired range as a function of the deposition temperature as well as the carbon content of the gas mixture during SIC layer formation. After the silicon carbide layer is formed on the substrate, a layer of energy sensitive resist material is formed thereon. A pattern is defined in the energy sensitive resist at a wavelength less than about 250 nm. Thereafter, the pattern defined in the energy sensitive resist material is transferred into the silicon carbide layer. After the silicon carbide layer is patterned, such pattern is optionally transferred into the substrate.